1. Field of the Invention
The present invention relates to a display apparatus and a method of driving a display apparatus, and more particularly, to a display apparatus having a display device that includes a driving circuit and a current-driven type light emitting portion and a method of driving the display apparatus.
2. Description of the Related Art
Display devices each having a current-driven type light emitting portion and display apparatuses including related display devices are known. For example, display devices each including an organic electroluminescent light emitting portion using the electroluminescence of an organic material have called attention as display devices that can emit light with high luminance through low-voltage DC driving.
Similarly to liquid crystal display apparatuses, as the driving methods of the display apparatuses including a display device having a current-driven light emitting portion, a simple matrix type and an active matrix type are known. The active matrix type has a disadvantage of a complicated structure but has an advantage of capable of raising the luminance of an image and the like. The display device having a current-driven type light emitting portion that is driven by the active matrix further includes a driving circuit used for driving the light emitting portion, in addition to the light emitting portion.
In FIG. 2 of JP-A-2009-122352, a pixel circuit 2 that is configured by a light emitting device EL (it corresponds to a light emitting portion), a sampling transistor T1, a driving transistor T2, and a holding capacitor C1 is disclosed. In addition, in FIG. 1, a display apparatus including a pixel circuit 2 is disclosed.
In JP-A-2009-122352, in order to cancel the influence of the variations in a threshold voltage Vth of the driving transistor T2 on a drain current Ids flowing through a light emitting device EL, a threshold voltage correcting operation and a signal electric potential writing operation are performed during one horizontal scanning period. In addition, the difficulty in performing the threshold voltage correcting operation and the signal electric potential writing operation during one horizontal scanning period as the one horizontal scanning period is shortened due to high definition of the display apparatus or the like is disclosed (Paragraph No. 0011 and the like of JP-A-2009-122352).
In JP-A-2009-122352, a composite scanning period including a first period and a second period is set in accordance with a scanning period that is assigned to each of a plurality of scanning lines. During the first period, control signals are output altogether to the plurality of scanning lines, so that threshold voltage correcting operations are performed altogether. In addition, during the second period, control signals are sequentially output to the plurality of scanning lines, and the signal electric potential writing operations are sequentially performed (Paragraph No. 0012 and the like of JP-A-2009-122352).
In FIG. 14 of JP-A-2009-122352, an operation for a case where two horizontal scanning periods (2H) are composed is shown. During the first period, control signals P1 are output altogether to two scanning lines (N-th line and (N+1)-th line), and the threshold voltage correcting operations are performed altogether. Subsequently, during the second period, control signals P2 are sequentially output to two scanning lines, and the signal electric potential writing operations are sequentially performed. As input signals, Vofs is used during the first period, VSig1 is used during the first half of the second period, and VSig2 is used during the second half of the second period. A sampling transistor T1 (N) of the N-th line is in the conductive state in accordance with the control signal P2 and samples VSig1. Subsequently, the sampling transistor T1 (N+1) of the (N+1)-th line is in the conductive state in accordance with the control signal P2 and samples VSig2 (Paragraph No. 0038 and the like of JP-A-2009-122352).
In the threshold voltage correcting operation, as shown in FIG. 7 of JP-A-2009-122352, Vofs is applied to the gate of the driving transistor T2 through the sampling transistor T1 that is in the conductive state, and the first electric potential Vcc is applied to the drain of the driving transistor T2. The electric potential of the source of the driving transistor T2 rises as time elapses, and the driving transistor T2 is cut off (in the non-conductive state), and the electric potential of the source thereof becomes (Vofs−Vth) (FIG. 8, Paragraph No. 0028, and the like of JP-A-2009-122352).